Inhalt

•  
  Introduction
•  
   Motivation
•  
   Overview
•  
   Processor aspects
•  
  Scientific contributions
•  
   Language concepts
•  
   Generation methods
•  
   Processor implementations
•  
   System overview
•  
   Evolution of ViDL and its generators
•  
   Areas of expertise
•  
  Fundamentals
•  
   Instruction set architectures
•  
   ARM
•  
   MIPS
•  
   OISC — One instruction set computer
•  
   Design scenarios
•  
   Domain specific languages
•  
   Compilation methods
•  
   Front-end
•  
   Middle-end
•  
   Back-end
•  
   Compiler framework
•  
   Type systems
•  
   Subtyping
•  
   Tuples
•  
   Signatures
•  
   Polymorphic types
•  
   Polymorphic functions
•  
  Term rewriting systems
•  
   Term
•  
   Rewrite rules
•  
   Termination and confluence
•  
   Microarchitecture
•  
   Storages
•  
   Datapath
•  
   Pipeline
•  
   Execution order
•  
   Forwarding
•  
   Interlocking
•  
   Branch prediction
•  
  Related approaches
•  
   Taxonomy of ISA specification languages
•  
   Notation in ISA manuals
•  
   ARM manual
•  
   Review
•  
  ISP
•  
   State
•  
   Aliases
•  
   Instruction encoding
•  
   Activations
•  
   Actions
•  
   Data-types
•  
   Review
•  
   nML
•  
   State
•  
   Instruction set
•  
   Modeling of instruction sets
•  
   Review
•  
   ASIP Meister/PEAS-III
•  
  Lisa
•  
   Storages
•  
   Instruction set
•  
   Hardware sharing
•  
   Pipeline
•  
   Complexity of language
•  
   Practical application
•  
   ISDL
•  
   Expression
•  
   Tensilica instruction extension (TIE)
•  
   State
•  
   Instruction semantics
•  
   Hardware sharing
•  
   Datapath scheduling
•  
   DPG — Datapath generator
•  
   ViDL — Versatile ISA description language
•  
   A ViDL example
•  
   Structure of a specification
•  
   Abstraction from microarchitecture
•  
  Instructions
•  
   Encoding
•  
   Semantics
•  
   Functional concepts
•  
   Functions
•  
   Polymorphism
•  
   Closures
•  
   Recursion
•  
   Name binding
•  
   Tuples
•  
   Vectors
•  
   Review of concepts
•  
   Epsilon logic
•  
   Operating on epsilon logic
•  
   Review
•  
   Delays
•  
   Causality
•  
   Review
•  
   Architectural interfaces
•  
   Mapping
•  
   Review
•  
   Type system
•  
   Types
•  
   Type inference
•  
   Evaluation
•  
   Transfer primitives
•  
   Library
•  
   Primitive
•  
   Generic primitives
•  
   Review
•  
  Design patterns
•  
   Partial memory accesses
•  
   Status registers
•  
   Processor-mode sensitive registers
•  
   Register windowing
•  
   Dynamically reconfigurable register files
•  
   Register pairs
•  
   Constant register
•  
   Embedded program counter
•  
   Branch
•  
   SIMD instructions
•  
   Conditional execution
•  
   Complex operand encodings
•  
   Addressing modes
•  
  Generators
•  
   Processing of ViDL
•  
   Name analysis
•  
   Optimizations
•  
   Translation of architectural interfaces
•  
   Analysis of instruction encoding
•  
   Intermediate representation
•  
   Instruction DFGs
•  
   DFG simplification
•  
   Origin information
•  
   Term rewriting system
•  
   Isomorphism
•  
   Applications
•  
   Origin information
•  
   Integer arithmetic
•  
   Rule sets
•  
   Bit-widths
•  
  Transformations and optimizations
•  
   Partial evaluation
•  
   Epsilon transformation
•  
   Methods for generating simulators
•  
   Structure of simulator
•  
   Bit-strings
•  
   Decoding
•  
   Implementing instruction semantics
•  
   Transactions
•  
   Methods for generating processors
•  
   Register port allocation
•  
   Operation pipelining
•  
   Timing
•  
   Port scheduling
•  
   Operation scheduling
•  
   Pipeline registers
•  
   Forwarding circuit
•  
   Interlocking
•  
   Branch prediction
•  
  Evaluation
•  
   Evaluation process
•  
  ViDL
•  
   Real world instruction sets
•  
   Efficient specification
•  
   Usability
•  
   Rapid exploration of instruction sets
•  
   Restrictions
•  
   Generator speed
•  
   Simulator generator
•  
   Setup
•  
   Characteristic instructions
•  
   ISA width
•  
   Width of simulator code
•  
   Generator optimizations
•  
  Processor generator
•  
   Setup
•  
   Overview of generated processors
•  
   Exploration of microarchitecture
•  
   Comparison to handcrafted processors
•  
   OISC — A simple processor
•  
   Wide instruction sets
•  
   Register ports
•  
   Structure of generated pipeline
•  
   Latencies and penalties
•  
   Resolution of hazards
•  
   Generating waveform definitions for ModelSim
•  
  DNACore — A case study on ISE
•  
   Development process
•  
   Algorithm
•  
   Instruction set extension
•  
   Specification in ViDL
•  
   Dynamic behavior of processor
•  
   Results and remarks
•  
   Summary
•  
   Conclusion