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Reconfigurable accelerators in the world of general-purpose computing / by Tobias Kenter. Paderborn, 2016
Content
Abstract
Zusammenfassung
Contents
List of Tables
List of Listings
List of Figures
Introduction
Motivation
Contributions of this Thesis
Thesis Structure
Computing Concepts, Trends and Domains
Compute Devices: Basic Terms and Concepts
Target Metrics
Instruction-Programmable Processors
Computing in Circuits
Field-Programmable Gate Arrays
Trends in Technology, Architectures and Devices
Scaling in Process Technology: Continuity and Changes
Impact on Processor Architecture
Accelerators
FPGA Accelerators
Computing domains and markets
General-Purpose and Special-Purpose Computing
Complex Embedded Systems in Automotive
Modern Smartphones
FPGAs in Special-Purpose Computing and Beyond
Markets and Workloads of General-Purpose Computing
Personal and Mobile Computers
Sever Class Computers
Opportunity Matrix
Chapter Conclusion
The Case for general-purpose adoption of FPGAs with the help of Overlay-Architectures
Between Performance and Productivity Walls
Productivity of General-Purpose Architectures
Impact of System Architectures
FPGA Productivity
Three Pillars for General-Purpose FPGAs
FPGA Overlays
Instruction-Programmable Overlays
Reconfigurable Hardware beyond FPGAs
Structurally Programmable Overlays
Chapter Conclusion
Stereo-Matching Kernels on Overlay and Custom Designs
Introduction to the Stereo-Matching Problem
Stereo-Matching Algorithm with Inherent Parallelism
Cost Initialization
Cost Aggregation
Scanline Optimization
Disparity Refinement
Software Implementation
Utilized FPGA Platforms and Programming Models
Maxeler Platform and Programming Paradigm
Convey HC-1 Platform with Vector Processor Overlay
Comparison of FPGA Platforms
Kernel-Centric Acceleration
Kernel-Designs for two FPGA platforms
Aggregation Kernels
Scanline Kernels
Synthesis and Integration
Kernel Summary
Experimental Setup
Evaluated Systems
Input Data
Evaluation and Comparisons
Stereo-Matching System Performance
Platform Overheads
Kernel Performance
Quantifying Overlay Overheads through Hardware-Normalization
Overheads by Kernel Groups
Estimates on Design Efforts
Limitations of the Comparison
Related Work
Chapter Conclusion
Compilation and Runtime Techniques for FPGA Accelerators
Motivation
Approach
Toolflow for Heterogeneous Executables
Code Extraction
Vectorization
Runtime Decisions
Experimental Setup
Evaluation
Comparison to Hand-Written Kernels of Chapter 4
Further Experiments
Related Work
Excursion to Offloading Decisions at Runtime
System-Level Scheduling and Task Migration
Chapter Conclusion
CPU-accelerator System Integration
Motivation
Proposed Architecture
Relation to Existing Architectures
Method and Framework
Estimation Model
Partitioning Approach
Design Space Exploration
Speedups per benchmark
Memory integration
Accelerator Size
Execution Efficiency
Interface Latency
Related Work
Chapter Conclusion
Conclusion
Summary
Outlook
Towards a Library of Overlay Architectures and Tools
And Beyond
Acronyms
Author's publications
Bibliography
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