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Gnokam Defo, Gilles Bertrand: A framework for assertion-based timing verification and PC-based restbus simulation of automotive systems. 2015
Inhalt
Introduction
Motivation
Automotive system innovation
Simulation
Modeling
Problem statement
Restbus simulation for early functional validation
Data synchronization between simulator and hardware
Specification of timing constraints
Research contribution
Structure of this thesis
Foundation
Automotive Control Systems
Open-Loop Control
Closed-Loop Control
Design of Automotive Control Systems
Classification of Real-Time systems
Design Methodology (AUTOSAR)
Timing Modeling with TADL2
Testing and Verification
Automotive Vehicle Netwoks
Controller Area Network (CAN)
FlexRay
Design of Electronic Systems
Design Modeling with IP-XACT
Design Modeling Language with SystemC
Formal Property Specification Language with PSL
Related Work
IP-XACT
Extensions of the IP-XACT Schema
Modeling and simulation of embedded automotive software
Restbus Simulation
Modeling and simulation with SystemC
Design Framework for IP Reuse and Integration
AUTOSAR Vs. SystemC
Verification of temporal properties
Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation
Verifying SystemC using a software model checking approach
Monitoring Temporal SystemC Properties
Dynamic Assertion-Based Verification
Assertion-based Verification of temporal properties
Methodology
Overall design flow
Phase 1: Component assembly
Phase 2: Timing requirements formalization and Code generation
Phase 3: Timing verification
Phase 4: Model equivalence check
Phase 5: Restbus simulation
Restbus simulator
Architecture of the Restbus Simulator
The SystemC simulator
Adapter
Assertion-Based Timing Verification
Background
Motivation
PSL, Sequential Extended Regular Expression (SERE)
IP-XACT
DataEvents and Event chains
tadl2: Notation
Formalizing Timing Requirements
Reason for using both tadl2 and psl
RepeatConstraint
StrongDelayConstraint
RepetitionConstraint
DelayConstraint
SporadicConstraints
Periodic constraints
Synchronization Constraint
Order Constraint
Verification of the timing properties
Summary
Verification of timing properties: case study Brake-By-Wire
Functional decomposition of the BBW model
Instrumenting of the simulation model
Reference model
Specifying the timing requirements
Evaluation results
Repeat, StrongDelay and Repetition timing constraints
Evaluation of the AgeConstraint and ReactionConstraint
Evaluation of synchronization related timing Constraints
Summary and discussion
Synchronization
Background
Data smoothing: Robust LOWESS/LOESS
Multirate Systems
Downsampling
Our synchronization approach
Upsampling
Downsampling
Main phase
Initialization phase
Downsampling with peak detection
Summary
Evaluation of Synchronization approach
Evaluation platform
System Overview
Hardware architecture
Software architecture
Applied tools
Evaluation results
Impact of the SendQueue-size on transmission delay
Variation of the smoothing parameter of Robust LOWESS
Impact of the SendQueue size on peak sequence detection
Impact of the data processing rate ratio on data synchronization
Summary
Conclusion
Summary
Outlook
Synchronization
Timing verification
Verification unit
Pictorial representation of the IP-XACT Schema Extensions
Diagrams
Elements and sequences
Elements and choices
Elements, attributes, groups, and attributeGroups
Wildcards
List of Acronyms
List of Figures
List of Tables
List of Own Publications and Bibliography
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