Inhalt

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   Abstract
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   Zusammenfassung
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   Acknowledgments
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   Contents
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   List of Figures
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   List of Tables
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   Listings
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   Acronyms
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   Foundation
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  1 Introduction
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   1.1 Motivation
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   1.2 Goal of the Thesis
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   1.3 Thesis Contributions
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   1.4 Thesis Outline
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  2 Basics
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   2.1 Smart-Card SOC
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   2.2 Object Files
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   2.3 The ELF Object File Format
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   2.4 Program Representation
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   2.4.1 Control Flow Graph
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   2.4.2 Call Graph
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   2.5 Data Flow Analysis
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   2.5.1 Data Flow Analysis Equations
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   2.5.2 Data Flow Problems
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   2.6 Contexts
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   2.6.1 Graphs with Context
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   2.6.2 Example
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   2.7 Summary
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  3 Related Work
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  3.1 Binary Analysis Approaches
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   3.1.1 Link-Time Optimization
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   3.1.2 Problems solved by Binary Analysis
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  3.2 Program Analysis Problems
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   3.2.1 Code Discovery
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   3.2.2 Self modifying code
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   3.2.3 Indirect Control Flow Target Detection
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   3.2.4 Detecting Idioms
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  3.3 Tools
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   3.3.1 Binary Decoding
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   3.4 Reconfigurable/Adaptable Systems
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   3.4.1 Structural Reconfiguration Mechanisms
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   3.5 Conclusion
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   The Approach
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  4 Legacy Code Reconfiguration
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   4.1 Requirements
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   4.2 Methodology
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   4.3 Consistency Preservation
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   4.3.1 Integrity
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   4.3.2 Consistency
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   4.3.3 State-Invariant
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   4.4 Architecture Restrictions of this Thesis
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   4.5 Open Problems
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  5 Control Flow Reconstruction
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   5.1 Building the Control Flow Graph
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   5.1.1 Interprocedural Control Flow Graph
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   5.1.2 Basic Block Augmentation
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   5.1.3 Indirect Control Flow Target Resolution
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   5.1.4 Safe Over-approximation
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   5.2 Summary
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  6 Component Model
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   6.1 Defining Reconfiguration Components
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   6.2 Reconstructing the Application Semantics
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   6.3 Generating the High-Level Annotated Control Flow Graph
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   6.3.1 High Level Expression Detection and Normalization
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   6.3.2 Memory Access Patterns
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   6.3.3 Arithmetic and Binary Patterns
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   6.3.4 High Level Variable Substitution
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   6.3.5 Global Variable Detection
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   6.4 Constraint-based Component Identification
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   6.5 Ensuring Disjoint Components
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   6.6 Summary
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  7 Runtime Reconfiguration
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   7.1 The Reconfiguration Architecture
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   7.2 The Reconfiguration Protocol
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  7.3 Reconfiguration Activities
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   7.3.1 Memory Management
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   7.3.2 Replacement Strategy
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   7.3.3 Indirection Layer
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   7.4 Operating System Integration
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   7.5 Real Time Characteristics
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   7.6 Summary
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  8 Component Optimization
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   8.1 Target System Restrictions / Notation
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   8.2 Optimization Steps
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   8.2.1 Component Partitioning
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   8.2.2 Component Merging
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   8.3 Calculating the Worst Case Blocking Time
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   8.3.1 Efficient WCET Calculation by Path Enumeration
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   8.3.2 Handling Cyclic Reconfigurations
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   8.3.3 Speedup of the Algorithm
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   8.3.4 Quality of the Estimation
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   8.4 Design Space Exploration
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   8.5 Summary
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  9 Binary Transformation
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   9.1 Modification Flow
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   9.2 ELF File Modification
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   9.2.1 Instrumentation Code
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   9.2.2 Data Duplication
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   9.2.3 Additional Linker Symbols
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   9.3 Summary
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   Evaluation
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  10 Evaluation
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   10.1 Case Study - SmartCard IPStack
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   10.1.1 Design Time Overhead
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   10.1.2 Reconfiguration Manager Binary Overhead
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   10.1.3 Component Extraction
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   10.1.4 Reconfiguration Delay Function
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   10.2 Design Space Exploration
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   10.3 Summary
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  11 Conclusion and Future Work
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   11.1 Thesis Summary
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   11.2 Outlook
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   Appendix
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  A Appendix
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   A.1 Mathematical Notation
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   A.2 Additional Path Enumeration Considerations
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   A.3 Calling Convention (RC_ABI)
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   A.4 System Constraint Language ABNF
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   A.5 Evaluation Design Points
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   A.6 The ARMv4(t) ISA
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   Bibliography
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   Declaration