High-speed MOS ICs for a signal processor input interface of an optical synchronous QPSK receiver and related clock distribution issues / Vijitha Rohana Herath. 2009
Content
- Dedication
- abstract_d
- abstarct_e
- Table of Content new
- PhD_dissert_chap
- 1.1 Background
- 1.2 Motivation
- 1.3 Use of CMOS Technology in High-Speed Optical Communication Systems
- 1.4 Organisation of Dissertation
- 2.1 Introduction
- 2.2 Digital Modulation Formats and Detection Techniques for Optical Communication
- 2.2.1. Optical Transmission System Performance Parameters
- 2.2.2. Receiver Concepts in Optical Fiber Communication
- 2.3 An Introduction to the Optical Synchronous QPSK (synQPSK) Transmission System
- 2.3.1. QPSK Transmitter
- 2.3.2. Coherent QPSK Receiver
- 2.3.3. Carrier and Data Recovery Algorithm
- 2.3.4. Electronic Polarization Control
- 2.4 CMOS DSP Unit Architecture
- 3.1 Introduction
- 3.2 Overview of the 130 nm CMOS Process
- 3.3 The Design of On Chip and on Ceramic Board Transmission Lines
- 3.3.1. Microstrip Line (MS-line)
- 3.3.2. Co-planar Waveguide with Ground Plane (CPWG)
- 3.3.3. Edge-Coupled Co-planar Waveguide with Ground Plane(ECCPWG)
- 3.4 Full Custom Design of Static Frequency Divider and 1:2 DEMUX ICs
- 3.5 Full Custom Design of 5bit (5×2 channel) 10 Gbit/s 1:8 DEMUX
- 3.5.1. Design of Buffers, Latches, and Logic Interface
- 3.5.2. Design of 1:8 DEMUX
- 3.5.3. Clock Distribution System Design
- 3.5.4. Layout Design
- 3.5.5. Simulation and Test Results
- 3.6 Full Custom Design of 5 bit (5×4 channel) 10 Gbit/s 1:8 DEMUX
- 3.7 Investigating Ultra High Speed Capabilities of the 130 nm CMOS Process
- 4.1 Introduction
- 4.2 Clock Skew Modeling
- 4.3 Mean Skew Estimation Algorithm
- 4.4 Results